1. Field of the Invention
The present invention generally relates to electronic logic circuits, and more particularly to a method of providing a safe operating mode for dynamic logic circuits, making them less susceptible to failures caused by noise.
2. Description of the Related Art
Modern digital electronic devices use a variety of logic circuits to accomplish various tasks. For example, microprocessors have execution units that are composed of a multitude of such logic circuits as AND, OR, NAND, NOR, XOR, and NOT gates. These logic circuits operate on input binary values to produce output binary values, i.e., a given value (signal) is either in a "low" voltage state (a value of zero) or a "high" voltage state (a value of one). The exact voltage of a high or low signal may vary considerably, and circuits are designed to be tolerant of margins about a nominal value. For example, conventional transistor-transistor-logic (TTL) logic levels use a voltage threshold of 1.4 volts, with a margin of 0.6 volts about the threshold, i.e., a high voltage state can be as low as 2.0 volts, and a low voltage state can be as high as 0.8 volts. Conventional circuitry using complementary metal-oxide semiconducting (CMOS) technology typically provides a voltage threshold between 2.0 and 3.0 volts.
There are generally two types of logic circuits, static and dynamic. Static circuits are typically constructed with elements that indefinitely remain in a given binary state (1 or 0) until the information in the element is intentionally changed, or the power to the circuit is shut off, so static circuitry does not need to be precharged. Dynamic circuits, in contrast, store information in capacitors, which can hold data for only a few milliseconds, so dynamic circuits must be regularly precharged using external circuitry.
A generic dynamic logic circuit is shown in FIG. 1. Dynamic logic circuit 10 includes a precharge device in the form of a p-type field-effect transistor (PFET) 12. The gate of PFET 12 is connected to the clock signal, its source is connected to the power supply (V.sub.dd), and its drain is connected to the logic network 14. A feedback or half-latch device in the form of another PFET 16 is connected in parallel with transistor 12, i.e., the source of transistor 16 is connected to V.sub.dd and its drain is also connected to logic network 14. The precharge node (the drains of transistors 12 and 16) is provided as an input to an inverter 18 whose output provides the output of the circuit, and which is connected to the gate of transistor 16. Logic network 14 is connected to ground via an evaluate device in the form of an n-type field-effect transistor (NFET) 18, whose gate is connected to the clock signal. The details of logic network 14 depend upon the type of logic circuit to be provided. For example, in a 2-input AND gate, the logic network consists of two serially connected NFETs, whose gates are respectively connected to the two inputs. Dynamic logic offers significant advantages over static logic, particularly in performance (speed) and required area. It is accordingly desirable to use dynamic logic to implement as much of the logical function as possible in a very large scale integrated (VLSI) chip design.
Logic circuits can generate erroneous signals, i.e., where the voltage level shifts beyond a threshold value, due to various reasons, such as a defective component (transistor, resistor, etc.), leakage, or noise. Dynamic logic is particularly sensitive to electrical noise. Inputs to dynamic logic circuits can effectively turn "on" due to noise and cause the logic to evaluate improperly. Usually, a charge is stored during a precharge phase of operation and then conditionally discharged during an evaluation phase of operation. However, this stored charge can be accidentally degraded or destroyed due to a variety of leakage or noise mechanisms, including capacitive coupling to adjacent signals, charge sharing, subthreshold conduction through the logic transistors, and conduction through the logic transistors due to noise on the inputs. If enough of the charge stored on the dynamic node is lost due to one or more of these mechanisms, the output of the dynamic logic gate with transition to the opposite state of the correct value. This error can propagate and cause a complete failure of the design.
Failures in the field are clearly undesirable, but failures during development of a device (such as a processor) can also be very difficult to isolate and identify, often extending development cycles and prolonging product introduction. Noise problems in general are difficult to detect because of their dependency on environmental conditions, processing variations, and data, and this difficulty applies as well to noise problems which cause dynamic circuits to fail. Unlike a straightforward long-path performance failure or an AC defect failure, noise problems cannot be made to disappear simply by extending cycle time.
In light of the foregoing, it would be desirable to provide a method of remedying noise problems in dynamic circuits, particularly to allow hardware and software development to progress until a more permanent (high-performance) solution to the noise problem can be designed and implemented. It would be further advantageous if the dynamic circuits could be made to selectively operate in a safe mode to facilitate detection of a noise problem, but the circuitry required for the safe mode should not have an impact so adverse as to negate the advantages of dynamic circuits over static circuits.